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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>The Xilinx HDMI PHY (HDMIPHY) driver. </p>
<p>This driver supports the Xilinx HDMI PHY IP core.</p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
           dd/mm/yy
</p>
<hr/>
<p>
1.0   gm   10/12/18 Initial release.
1.1   ku   24/07/20 Removed GTHE3 parameters
                    Added MMCM parameters to support MAX Rate
1.2   ku   28/04/21 Updated Min Max limits for DRU Refclk
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gab2369998b0e4635bced93881e51cc8fe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab2369998b0e4635bced93881e51cc8fe">XHdmiphy1_ClkDetEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:gab2369998b0e4635bced93881e51cc8fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the HDMIPHY's detector peripheral.  <a href="group__xhdmiphy1.html#gab2369998b0e4635bced93881e51cc8fe">More...</a><br/></td></tr>
<tr class="separator:gab2369998b0e4635bced93881e51cc8fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac2f877b2581399c3344d1555d05df2df"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac2f877b2581399c3344d1555d05df2df">XHdmiphy1_ClkDetTimerClear</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gac2f877b2581399c3344d1555d05df2df"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the clock detector TX/RX timer.  <a href="group__xhdmiphy1.html#gac2f877b2581399c3344d1555d05df2df">More...</a><br/></td></tr>
<tr class="separator:gac2f877b2581399c3344d1555d05df2df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a055146c6b3aa1da1991a0041dc11f7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5a055146c6b3aa1da1991a0041dc11f7">XHdmiphy1_ClkDetSetFreqLockThreshold</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u16 ThresholdVal)</td></tr>
<tr class="memdesc:ga5a055146c6b3aa1da1991a0041dc11f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the clock detector frequency lock counter threshold value.  <a href="group__xhdmiphy1.html#ga5a055146c6b3aa1da1991a0041dc11f7">More...</a><br/></td></tr>
<tr class="separator:ga5a055146c6b3aa1da1991a0041dc11f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa113dd9ce96c346ef9b757947eb340fe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa113dd9ce96c346ef9b757947eb340fe">XHdmiphy1_ClkDetAccuracyRange</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u16 ThresholdVal)</td></tr>
<tr class="memdesc:gaa113dd9ce96c346ef9b757947eb340fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the clock detector accuracy range value.  <a href="group__xhdmiphy1.html#gaa113dd9ce96c346ef9b757947eb340fe">More...</a><br/></td></tr>
<tr class="separator:gaa113dd9ce96c346ef9b757947eb340fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafaece55136a95db26cf37edcd53c96f8"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafaece55136a95db26cf37edcd53c96f8">XHdmiphy1_ClkDetCheckFreqZero</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gafaece55136a95db26cf37edcd53c96f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks clock detector RX/TX frequency zero indicator bit.  <a href="group__xhdmiphy1.html#gafaece55136a95db26cf37edcd53c96f8">More...</a><br/></td></tr>
<tr class="separator:gafaece55136a95db26cf37edcd53c96f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga46cb7e8a6cc10a61bbfb7126f85e8cec"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga46cb7e8a6cc10a61bbfb7126f85e8cec">XHdmiphy1_ClkDetSetFreqTimeout</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u32 TimeoutVal)</td></tr>
<tr class="memdesc:ga46cb7e8a6cc10a61bbfb7126f85e8cec"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets clock detector frequency lock counter threshold value.  <a href="group__xhdmiphy1.html#ga46cb7e8a6cc10a61bbfb7126f85e8cec">More...</a><br/></td></tr>
<tr class="separator:ga46cb7e8a6cc10a61bbfb7126f85e8cec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbffa1bd1304f2f69a32aa1a22573052"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gacbffa1bd1304f2f69a32aa1a22573052">XHdmiphy1_ClkDetTimerLoad</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u32 TimeoutVal)</td></tr>
<tr class="memdesc:gacbffa1bd1304f2f69a32aa1a22573052"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function loads the timer to TX/RX in the clock detector.  <a href="group__xhdmiphy1.html#gacbffa1bd1304f2f69a32aa1a22573052">More...</a><br/></td></tr>
<tr class="separator:gacbffa1bd1304f2f69a32aa1a22573052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ccf265013fcb1e013775dc9a8563c87"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5ccf265013fcb1e013775dc9a8563c87">XHdmiphy1_DruReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Reset)</td></tr>
<tr class="memdesc:ga5ccf265013fcb1e013775dc9a8563c87"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the DRU in the HDMIPHY.  <a href="group__xhdmiphy1.html#ga5ccf265013fcb1e013775dc9a8563c87">More...</a><br/></td></tr>
<tr class="separator:ga5ccf265013fcb1e013775dc9a8563c87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b7a69d580eaac17960b977851aead25"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7b7a69d580eaac17960b977851aead25">XHdmiphy1_DruEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Enable)</td></tr>
<tr class="memdesc:ga7b7a69d580eaac17960b977851aead25"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enabled/disables the DRU in the HDMIPHY.  <a href="group__xhdmiphy1.html#ga7b7a69d580eaac17960b977851aead25">More...</a><br/></td></tr>
<tr class="separator:ga7b7a69d580eaac17960b977851aead25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5da59924fa5189f7141d950e6d31a50"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab5da59924fa5189f7141d950e6d31a50">XHdmiphy1_DruGetVersion</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gab5da59924fa5189f7141d950e6d31a50"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the DRU version.  <a href="group__xhdmiphy1.html#gab5da59924fa5189f7141d950e6d31a50">More...</a><br/></td></tr>
<tr class="separator:gab5da59924fa5189f7141d950e6d31a50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02899710d93b44ffa5d6f87637d67809"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga02899710d93b44ffa5d6f87637d67809">XHdmiphy1_DruSetCenterFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u64 CenterFreqHz)</td></tr>
<tr class="memdesc:ga02899710d93b44ffa5d6f87637d67809"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the DRU center frequency.  <a href="group__xhdmiphy1.html#ga02899710d93b44ffa5d6f87637d67809">More...</a><br/></td></tr>
<tr class="separator:ga02899710d93b44ffa5d6f87637d67809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c7a948926fede8a6548c6cffe5fc830"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga4c7a948926fede8a6548c6cffe5fc830">XHdmiphy1_DruCalcCenterFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga4c7a948926fede8a6548c6cffe5fc830"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the center frequency value for the DRU.  <a href="group__xhdmiphy1.html#ga4c7a948926fede8a6548c6cffe5fc830">More...</a><br/></td></tr>
<tr class="separator:ga4c7a948926fede8a6548c6cffe5fc830"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae9070f7158ccb8538edf80a5ec4c8da6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae9070f7158ccb8538edf80a5ec4c8da6">XHdmiphy1_HdmiGtDruModeEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:gae9070f7158ccb8538edf80a5ec4c8da6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the GT RX CDR and Equalization for DRU mode.  <a href="group__xhdmiphy1.html#gae9070f7158ccb8538edf80a5ec4c8da6">More...</a><br/></td></tr>
<tr class="separator:gae9070f7158ccb8538edf80a5ec4c8da6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51d10d93fa76ebe0c031600b61955d4d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga51d10d93fa76ebe0c031600b61955d4d">XHdmiphy1_PatgenSetRatio</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, u64 TxLineRate)</td></tr>
<tr class="memdesc:ga51d10d93fa76ebe0c031600b61955d4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock.  <a href="group__xhdmiphy1.html#ga51d10d93fa76ebe0c031600b61955d4d">More...</a><br/></td></tr>
<tr class="separator:ga51d10d93fa76ebe0c031600b61955d4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe6529e3429c7199f87f7f8fc7f43fe0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafe6529e3429c7199f87f7f8fc7f43fe0">XHdmiphy1_PatgenEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, u8 Enable)</td></tr>
<tr class="memdesc:gafe6529e3429c7199f87f7f8fc7f43fe0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables or disables the Pattern Generator for the GT Channel 4 when it isused to generate the TX TMDS Clock.  <a href="group__xhdmiphy1.html#gafe6529e3429c7199f87f7f8fc7f43fe0">More...</a><br/></td></tr>
<tr class="separator:gafe6529e3429c7199f87f7f8fc7f43fe0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f26c79a098ddb33f610f5a88efc140e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga1f26c79a098ddb33f610f5a88efc140e">XHdmiphy1_HdmiIntrHandlerCallbackInit</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga1f26c79a098ddb33f610f5a88efc140e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the appropriate HDMI interupt handlers.  <a href="group__xhdmiphy1.html#ga1f26c79a098ddb33f610f5a88efc140e">More...</a><br/></td></tr>
<tr class="separator:ga1f26c79a098ddb33f610f5a88efc140e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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